1. Technical Field
The present invention relates generally to memory design evaluation circuits, and more particularly to a memory circuit having an oscillator circuit that has a frequency that accurately reflects internal read timing of a memory cell.
2. Description of the Related Art
Storage cell speed, circuit area and environmental operating ranges, e.g., supply voltage and temperature range, are critical limitations in today's processing systems and are predicted to become even more of a critical limitation as technologies move forward. In particular, static random access memory (SRAM) cells are used in processor caches and external storage to provide fast access to data and program instructions. Static storage cells are also used within processors and other digital circuits for storing values internally, for example, in processor registers.
With processor cycle frequencies reaching well above 4 Ghz, development of SRAM cells that can store and provide access to stored values within that period has become necessary. However, actually measuring the internal read timing of memory cells presents a challenge. In a typical storage cell, there is no mechanism for determining read timing of the cell itself, only the total delay including the wordline access and bitline read circuits. Probing the storage cell affects the operation of the storage circuit and therefore the results of any evaluation based on probing the cell. Test circuits can be built that simulate the operation of a storage cell for the purposes of cell read timing measurement, but are typically not integrated within the actual environment of a cell in a storage array, including bitline and wordline loading effects.
Memory cell timing for a combination of read and write delays has been evaluated using ring oscillator circuits or cascaded cell delay circuits wherein a large number of cells are cascaded. A ring oscillator may be formed with feedback of an output of the last cell to an input of the first cell, or a one-shot delay may be measured through the cascade of cells. The frequency at which the ring oscillator operates or the one-shot delay indicates the read/write cycle timing, which provides some measure of ultimate operating frequency and access times of the storage array. Typically, the cell design is then changed in subsequent design iterations having parameters adjusted in response to the results of the ring oscillator test.
However, the above-mentioned ring oscillator circuits and other delay-oriented circuits for performing delay tests do not provide an independent measure of read timing, since the inclusion of a cell in the oscillator ring or delay line requires that the cell values will be written in some manner to change the value in the next cell as a transition of the oscillation is propagated around the ring. Further, such circuits do not provide for measuring read current or read strength independent of the speed of a write operation.
It is therefore desirable to provide a test circuit and method for accurately measuring cell read timing independent of write timing under the load conditions of actual array. It is further desirable to provide a circuit and method that can measure read strength/read current directly. It is further desirable to provide such a test circuit that can be integrated within a production storage device.